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24AA52/24LCS52
3.0
FUNCTIONAL DESCRIPTION
4.4
Data Valid (D)
The 24XXX52 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XXX52
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
4.0
BUS CHARACTERISTICS
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
is not busy.
4.5
Acknowledge
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
Note: The 24XXX52 does not generate any
Acknowledge bits if an internal
4.1
Bus Not Busy (A)
programming cycle is in progress.
Both data and clock lines remain high.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
4.2
Start Data Transfer (B)
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
4.3
Stop Data Transfer (C)
on the last byte that has been clocked out of the slave.
In this case, the slave (24XXX52) will leave the data
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
line high to enable the master to generate the Stop
condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
(A)
(B)
(D)
(D)
(C)
(A)
SDA
Start
Condition
DS21166K-page 6
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
? 1996-2011 Microchip Technology Inc.
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